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| ST18952 DIGITAL SIGNAL PROCESSOR (DSP) CHIP PRELIMINARY DATA s s s Programmable D950 Core s Data calculation unit s Address calculation unit s Program control unit s Fast and flexible buses s 66MIPS - 15 ns instruction cycle time 16.5 Kwords data memory (RAM) 32 Kwords program memory (RA42 1714 01) s Interrupt controller s DMA controller s Serial input/output s Timer s Bus switch unit s Emulation unit s JTAG IEEE 1149.1 test access port TAP 16.5 Kwords data memory Emulation unit D950 core 32 Kwords program memory 2 Timers Bus switch unit 2 Serial I/O Interrupt controller DMA controller 12 January 98 The information in this datasheet is subject to change 42 1714 01 1/66 Table of Contents 1 2 3 4 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 D950Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 5.1 5.2 6 6.1 6.2 7 7.1 7.2 8 9 8.1 9.1 D950Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal memory resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Direct bus extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BSU operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BSU control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Switch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 SIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.1 SIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 External Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.1 System registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13 JTAG IEEE 1149.1 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14 Emulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15.1 DC Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15.2 DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 16 Y SPACE Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.2 Serial input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.3 Timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . 58 16.4 Bus switch unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2/66 1 Table of Contents 16.5 System control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16.6 DMA controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.7 Interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.8 Emulation unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.9 D950Core control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17 ST18952 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1 208 pin PQFP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.2 208 pin PQFP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3/66 ST18952 1 Introduction The ST18952 chip includes the SGS-Thomson D950 16-bit fixed point digital signal processor core, 16.5 Kwords of data memory, 32 Kwords of program memory, and the following on-chip peripherals: * * * * * * * Interrupt controller (ITC) DMA controller (DMA) Bus switch unit (BSU) Synchronous input/output (SIO) Timer (TIM) Emulation unit (EMU) Tap controller (TAP) It also includes an oscillator and a PLL for generation of the D950Core clock. The ST18952 is used on the D950 Emulation Card (called the D952 module) developed by SGS-Thomson. It can also be used for application development by customers. Custom development is eased by providing direct access to the D950 instruction and data buses to allow simultaneous access to external memories or peripherals (with wait-states). For full details of the D950Core refer to the D950Core datasheet (document number 42-1709). 4/66 2 ST18952 2 Pin Description The following tables detail the ST18952 pin set. There is one table for each group of pins. The tables detail the pin name, type and a short description of the pin function. Signal names have an overbar if they are active low, otherwise they are active high. Table 2.1 Pin name IDE0-15 IAE0-15 IRDE IWRE IBSE Direct I bus extension (35 pins) Type I/O O O O O Description Instruction data extension bus. Instruction address extension bus. I-extension bus read strobe. Active low. I-extension bus write strobe. Active low. I-extension bus strobe. Active low. Table 2.2 Pin name YDE0-15 YAE0-15 YRDE YWRE YBSE Direct Y bus extension (35 pins) Type I/O O O O O Description Y data extension bus. Y address extension bus. Y-extension bus read strobe. Active low. Y-extension bus write strobe. Active low. Y-extension bus strobe. Active low. Table 2.3 Pin name ED_XDE0-15 EA_XAE0-15 EIRD EIWR XBSE EYRD EYWR XRDE_EXRD XWRE_EXWR Direct X bus extension / bus extension through bus switch unit (39 pins) Type I/O O O O O O O O O Description Multiplexed input/output. Bus switch unit extension data bus or X data extension bus. Multiplexed output. Bus switch unit extension address bus or X address extension bus. BSU EIRD output BSU EIWR output X extension bus data strobe BSU EYRD output BSU EYWR output Multiplexed output. X-extension bus read strobe (XRDE) or BSU EXRD output. Multiplexed output. X-extension bus write strobe (XWRE) or BSU EXWR output. 5/66 ST18952 Table 2.4 Pin name P_ITRQ0-7 General purpose parallel port / Interrupt requests (8 pins) Type I/O Description Multiplexed input/output. Parallel port I/O or external interrupt request (ITRQ). Table 2.5 Pin name EXTAL XTAL MCLK CLK_MODE Clocks (6 pins) Type I O I I Description Oscillator input. Oscillator output. Nominal oscillator frequency is 27 MHz. Master clock input (use of external clock generator). Clock mode select input. When low the oscillator and internal PLL are enabled. The 950 receives its Master clock from the PLL at 5 times the oscillator frequency. When high the PLL is disabled. The D950 receives its master clock from MCLK. Instruction cycle. Asserted high for 1 CLKOUT cycle at the beginning of instruction cycle. Output clock (at input clock/2 frequency). INCYCLE CLKOUT O O Table 2.6 Pin name DTACK Bus control (3 pins) Type I Description Data transfer acknowledge input. Active low. It is combined in a OR gate with BSU DTACK output in order to generate the DTACK signal for the D950Core. It controls extension of bus cycles by insertion of wait-states when using external memory either through Bus-switch or direct extension. External Bus Hold request input. Active low. Hold acknowledge output. Active low. HOLD HOLDACK I O 6/66 ST18952 Table 2.7 Pin name RESET RESET_OUT LP LPACK MODE D950Core control (10 pins) Type I O I O I Description Reset input. Active low. Initializes the 950-Core to the RESET state. Reset output (system reset). Active low. Low power input. Active low. Low power acknowledge. Active low. Mode selection for Reset. 0: forces reset address to 0x0000 1: forces reset address to 0xFC00 Program memory read/write indicator. Valid coprocessor instruction output. Asserted low during the instruction cycle preceding a coprocessor instruction to enable operation of an external coprocessor. X stack read/write instruction flag. Y stack read/write instruction flag. I-bus direct transfer enable (to BSU peripheral). Active low. IRD_WR VCI O O STACKX STACKY IDT_EN O O I Table 2.8 Pin name ERQ IDLE Emulation unit (7 pins) Type I O Description Emulator Halt Request. Active low. Halts program execution and enters emulation mode. Output flag asserted high when the processor is halted due to an emulation halt request or a valid breakpoint condition.Asserted low when the processor is not Halted or during execution of an instruction under control of the emulator. Halt acknowledge. Active high. Asserted high when the processor is halted from an Emulator Halt request or when a valid Breakpoint condition is met. Snapshot. Active high. Asserted high when executing an instruction if Snapshot mode is enabled. Enable breakpoint on X address bus when high. Enable breakpoint on Y address bus when high. Enable breakpoint on I address bus when high. HALTACK O SNAP AXEBP AYEBP AIEBP_SCAN_EN O I I I 7/66 ST18952 Table 2.9 Pin name TDI TCK TMS TDO TRST JTAG IEEE 1149.1 test access port (5 pins) Type I I I O I Description Test data input. Test clock. Test mode select. Test data output. Test logic reset (also used for Emulator module). Active low. Table 2.10 Pin name DMA controller / Serial input/output (8 pins) Type I I/O I I/O O I/O O I/O Description DMA request 0 or SIO0 Receive data DMA request 1 or SIO0 Data clock DMA request 2 or SIO1 Receive data DMA request 3 or SIO1 Data clock DMA acknowledge 0 or SIO0 Transmit data DMA acknowledge 1 or SIO0 Frame synchronizer DMA acknowledge 2 or SIO1 Transmit data DMA acknowledge 3 or SIO1 Frame synchronizer DMARQ0/SRD0 DMARQ1/SCK0 DMARQ2/SRD1 DMARQ3/SCK1 DMACK0/STD0 DMACK1/SFS0 DMACK2/STD1 DMACK3/SFS1 8/66 ST18952 3 Functional Overview A block diagram of the ST18952 is shown below. The modules that comprise the ST18952 are outlined in this section and described in detail in the following sections. Figure 3.1 ST18952 block diagram Input clock + control Output clocks Control I/Os/ Port JTAG Port OSC + PLL I 8k x 16 (x 4) D950Core TAP Y 8k x 16 X/Y 0.5k x 16 Emulation unit X 8k x 16 Timer 0 Bus switch unit Ext. bus Timer 1 SIO 0 DMA controller SIO 1 Interrupt controller Direct extension buses 9/66 ST18952 D950Core The D950Core is a general purpose programmable 16-bit fixed point Digital Signal Processor Core. The main blocks of the D950Core include an arithmetic data calculation unit, a program control unit and an address calculation unit, able to manage up to 64k (program) and 128k (data) x 16-bit memory spaces. Memory One 32 Kword and two 8 Kword single port memories are included on-chip: * * * 32 Kword instruction memory on I space 8 Kword X-Data memory on X space 8 Kword Y-Data memory on Y space One 512 word dual port memory is shared on X and Y spaces. Memory can be extended off-chip for all three spaces in two ways: 1: Directly - Accesses to program and data memories can be performed simultaneously. Insertion of wait-states is necessary in case of nominal frequency work. 2: Through the bus switch unit - Accesses to the different external spaces are multiplexed and wait-states are added. Bus switch unit The bus switch unit (BSU) is a bi-directional switcher which switches the 3 internal buses (I, X and Y) to the external (E) bus. DMA controller The DMA controller manages data transfer between memories and external peripherals. There are four independent DMA channels. Transfers can occur on X/Y/I spaces (simultaneous transfers on X and Y spaces). Interrupt controller The interrupt controller (ITC) can manage up to eight external interrupts. Each source can be individually activated and programmed as edge or level triggered. A `pending interrupt' flag displays the source waiting for service (this flag is writable to allow a software interrupt capability). The priority of interrupts is programmable. Timers There are two timer (TIM) units on the ST18952. The timers enable interrupts to be generated after predefined periods of time. 10/66 ST18952 SIO There are two synchronous serial input/output (SIO) ports enable a link to serial devices such as codecs and to other processors. Oscillator and PLL A 27 MHz crystal can be used with the on-chip oscillator and PLL to provide the D950Core clock input. The PLL module multiplies the oscillator frequency by a factor of 10 and generates a 270 MHz signal. A programmable divider is connected to the PLL output to generate the D950 clock input. The division range is 2 to 256. Emulation unit and JTAG IEEE 1149.1 test access port The emulation unit (EMU) performs functions dedicated to emulation and test through the external IEEE 1149.1 JTAG interface. 11/66 ST18952 4 D950Core * * * Data Calculation Unit (DCU) Address Calculation Unit (ACU) Program Control Unit (PCU) The D950Core is composed of three main units. For full details of the D950 DSP core refer to the D950Core datasheet (document number 421709). These units are organized in an HARVARD architecture around three bidirectional 16-bit buses, two for data and one for instruction. Each of these buses is dedicated to an unidirectional 16-bit address bus (XA/YA/IA). An 8-bit general purpose parallel port (P0-P7) can be configured (input or output). A test condition is attached to each bit to test external events. The D950Core is controlled through interface pins related to interrupt, low-power mode, reset and miscellaneous functions. Figure 4.1 D950Core block diagram DATA CALCULATION OUTPUT CLKIN 6 16 16 16 16 3 16 16 UNIT YD-bus XD-bus ADDRESS CALCULATION XA-bus YA-bus UNIT PROGRAM CONTROL UNIT ID-bus IA-bus 11 CONTROL 8 PO/P7 14 TEST & EMULATION 12/66 VDD VSS PROGRAM MEMORY DATA MEMORY Control CLOCKS ST18952 Data buses (XD/YD and XA/YA) are provided externally. Data memories (RAM, ROM) and peripherals registers are mapped in these address spaces. Instruction bus (ID/IA) gives access to program memory (RAM, ROM). Each bus has its own control interface. Table 4.1 Data/instruction bus and corresponding address bus. Data/instruction bus XD YD ID Bidirectional Bidirectional Bidirectional 16-bit 16-bit 16-bit XA YA IA Corresponding address bus Unidirectional Unidirectional Unidirectional 16-bit 16-bit 16-bit Depending on the calculation mode, the D950Core DCU computes operands which can be considered as 16 or 32-bit, signed or unsigned. It includes a 16 x 16-bit parallel multiplier able to implement MAC-based functions in one cycle per MAC. A 40-bit arithmetic and logic unit, including an 8-bit extension for arithmetic operations, implements a wide range of arithmetic and logic functions. A 40-bit barrel shifter unit and a bit manipulation unit are included. The tables below illustrate the different types of word length and word format available for manipulation. Table 4.2 Summary of possible word lengths and formats 0 70 15 31 39 32 31 16 16 Format fractional integer signed unsigned signed unsigned 15 15 0 0 0 1-bit word 8-bit word 16-bit word signed / unsigned 32-bit word signed / unsigned 40-bit word signed / unsigned Minimum -1 0 - 32768 0 Maximum + 0.999969481 + 0.99996948 + 32767 + 65535 13/66 ST18952 4.1 D950Core registers Register BX MX BY MY POR PIR PCDR PCSR Function Modulo base address for X-memory space Modulo maximum address for X-memory space Modulo base address for Y-memory space Modulo maximum address for Y-memory space Port Output Register - 8LSB are significant, 8MSB are undefined when reading Port Input Register Port Control Direction Register Port Control Sensitivity Register PCDR The Port Control Direction register defines the data direction of each port pin. After reset, PCDR default value is 0 (Port pins are configured as inputs) 15 Bit PiD 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P7D P6D P5D P4D P3D P2D P1D P0D Function Port pin direction 0: Input port pin (def.) 1: Output port pin RESERVED (read: undefined, write: don't care) Bits 8 - 15 PCSR The Port Control Sensitivity register defines sensitivity of each port pin. After reset, PCSR default value is 0 (Port pins are configured as level-sensitive). 15 Bit PiS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P7S P6S P5S P4S P3S P2S P1S P0S Function Port pin sensitivity 0: Level sensitive (def.) 1: Edge sensitive RESERVED (read: undefined, write: don't care) Bits 8 - 15 14/66 ST18952 5 Memory 5.1 Internal memory resource One 32 Kword and two 8 Kword single port memories are included on-chip: * * * Instruction memory on I space from address 0 to 32767 (32 K) X-Data memory on X space from address 0 to 8191 (8 K) Y-Data memory on Y space from address 0 to 8191 (8 K) One 512 word dual port memory is shared on X and Y spaces, from addresses 8192 (8 K) to 8703 (8.5K). This is represented graphically below. Note: the first 256 addresses of the Y space are reserved for the D950 memory-mapped registers and for on-chip memory mapped peripherals. Memory can be extended off-chip for all three spaces in two ways: 1: Directly - Accesses to program and data memories can be performed simultaneously. Insertion of wait-states is necessary in case of nominal frequency work. 2: Through the bus switch unit - Accesses to the different external spaces are multiplexed and wait-states are added. The specific details on the operation of the BSU are described separately in "Bus Switch Unit" on page 18. Figure 5.1 Memory mapping X-memory FFFF 64k FFFF Y-memory 64k FFFF I-memory 64k External External External 8000 21FF 1FFF Internal DPRAM Internal SPRAM 0000 8.5k 8k 21FF 1FFF 0100 Internal DPRAM Internal SPRAM Registers 8.5k 8k Internal SPRAM 32k All addresses are hexadecimal External memory is accessed directly or through the bus switch 15/66 ST18952 5.2 Direct bus extension Direct extension for I-memory The internal program memory is used from address 0 to 32767 (32 K). Note, no detection is provided when an internal space is declared as an external one for the BSU. The I-bus direct transfer enable signal (IDT_EN) determines whether an access is made directly to external memory or via the BSU. If reset occurs with the MODE signal set to `1' (select reset address to xFC00), then * * if IDT_EN input = 0: access to external memory is through the BSU if IDT_EN input = 1: access to direct external memory space IAE/IBSE/IRDE/IWRE are always driven except in the case of an external HOLD request. Note: an external coprocessor will work only when executing program in the external space. IDE bus is an output only when a direct external write is detected. IDE bus is an input in the case of: * * an external memory read DMA (write) transfers between an external peripheral and internal memory Direct extension for X-memory The internal X memory is used from address 0 to 8703 (8.5 K). It is extended with external memory from address 8704 (8.5K) to 65535 (64K) with the XE bus extension. The direct extension is managed by the bus switch unit. When the EN_X bit of the BSU XER register (see "XER0/1: X-memory space control registers" on page 20) is set to `0', it generates only software wait-states and access is direct. If the EN_X bit is set to `1', data goes via the BSU. X extension and bus switch share the same I/O's. Direct extension for Y-memory The internal Y memory is used from address 0 to 8703 (8.5 K). It is extended with external memory from address 8704 (8.5 K) to 65535 (64 K) with the YE bus extension. Address 0 to 256 of the Y space are reserved for memory mapped registers. Note: The BSU and X direct extension share the same I/O, therefore extension of IE through the BSU is not possible when direct extension is selected for X/Y. Some combinations of the EN_I, EN_X and EN_Y bits of the BSU control registers IER/XER/YER are not allowed, as shown in Table 5.1 below. 16/66 ST18952 Table 5.1 EN_I 1 1 1 1 0 0 0 0 Possible BSU register settings Allowed or forbidden Allowed Allowed Forbidden (X direct & I/Y through BSU) Forbidden (X direct & I through BSU) Allowed Allowed Forbidden (X direct & Y through BSU) Allowed EN_X EN_Y Operation 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Exchanges enabled on I/X/Y spaces Exchanges enabled on I and X spaces Only DTACK generation on Y space Exchanges enabled on I and Y spaces Only DTACK generation on X space Exchanges enabled on I space Only DTACK generation on X and Y spaces Exchanges enabled on X and Y spaces Only DTACK generation on I space Exchanges enabled on X space Only DTACK generation on I and Y spaces Exchanges enabled on Y space Only DTACK generation on I and X spaces No exchange Only DTACK generation on I, X and Y spaces 17/66 ST18952 6 Bus Switch Unit The three memory spaces can be extended off-chip through the bus switch unit (BSU) peripheral. The figure below shows the layout of the D950Core BSU. Figure 6.1 D950Core Bus Switch Unit INTERNAL MEMORIES & PERIPHERALS 16 XD X MEM. Y MEM. P MEM. IRD/XRD/YRD 16 XA INTERNAL MEMORIES & PERIPHERALS ED BUS EA 16 16 2 2 2 D950Core IWR/XWR/YWR 16 YD SWITCH 16 YA EXRD/DS EXWR/RD UNIT EYRD/DS EYWR/RD EIRD/DS ID EIWR/RD DTACKin IDT_EN IA DTACK BSU_CLK RESET INTERNAL MEMORIES & PERIPHERALS IID/I XD/IYD DEID/DEXD/DEYD 16 IBS/XBS/YBS 16 AS-DSP VR02020A 6.1 BSU operation The BSU recognizes a bus cycle when a bus extension strobe (IBSE, XBSE or YBSE) goes active. The BSU decodes the address value to determine if an external memory access is requested on the I, X or Y-bus and generates the appropriate signals on the external bus side. The BSU generates software wait-states, depending on the setting of the control register. If more than one external memory access is attempted at one instruction cycle, they are serviced sequentially in the following order: I-bus, X-bus, Y-bus. Each external access requires one basic instruction clock cycle (2 CLKIN cycles), extended by, at least, one wait-state (2 CLKIN cycles). The number of wait-states can be extended, either by software with the BSU control registers (see Section 6.2), or by hardware with the DTACK input signal. 18/66 ST18952 6.2 BSU control registers The BSU is programmed by six control registers mapped in the Y-memory space. These define the type of memory used, internal to external boundary address crossing, exchange type (external direct or through the BSU) and software wait-states count. There are 2 registers per memory space, making it possible to define 2 sets of boundaries and wait state numbers. Figure 6.2 Default and user mapping examples 64K EXTE RNAL 64K EXTERNAL INTE RNAL1 63K 62K VALUE 1 INTERNAL1 VALUE 1 INTERNAL 0 VALUE 0 VALUE 0 INTERNAL0 0 DEFA ULT MAPPING (RESET) USER MAPPING (CAN CHANGE BY 1K STEP) 0 The BSU control registers include a reference address on bits 4 to 9, where the internal/ external memory boundary value is stored (see Figure 6.2), and software wait-states count on bits 0 to 3, allowing up to 16 wait-states. External addressing is recognized by comparing these address bits for each valid address from IA, XA and YA, to the reference address contained into the corresponding control register. If the address is greater or equal to the reference value, an external access proceeds. In the following register descriptions, `-' means RESERVED (read: 0, write: don't care). 19/66 ST18952 XER0/1: X-memory space control registers After reset, XER0/1 default values are 0x83EF/0x83FF 15 IM Bit W3:0 XA15:10 EN_X IM 14 EN_X 13 12 11 10 9 8 7 6 5 4 3 2 W2 1 W1 0 W0 XA15 XA14 XA13 XA12 XA11 XA10 W3 Function Wait state count (1 to 16) for off-chip access (X-memory space) X-memory space map for boundary on-chip or off-chip Enable for X-space data exchanges Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) YER0/1: Y-memory space control registers After reset, YER0/1 default values are 0x83EF/0x83FFI 15 IM Bit W3:0 YA15:10 EN_Y IM 14 EN_Y 13 12 11 10 9 8 7 6 5 4 3 2 W2 1 W1 0 W0 YA15 YA14 YA13 YA12 YA11 YA10 W3 Function Wait state count (1 to 16) for off-chip access (Y-memory space) Y-memory space map for boundary on-chip or off-chip Enable for Y-space data exchanges Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) IER0/1: Instruction memory control registers After reset, IER0/1 default values are 0x83EF/0x83FF or 0xC3EF/0xC3FF (the EN_I value depends on the IDT_EN input value 15 IM Bit W3:0 IA15:10 EN_I IM 14 EN_I 13 12 11 10 9 8 7 6 5 4 3 W3 2 W2 1 W1 0 W0 IA15 IA14 IA13 IA12 IA11 IA10 Function Wait state count (1 to 16) for off-chip access (I-memory space) I-memory space map for boundary on-chip or off-chip Enable for I-space data exchanges Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) 20/66 ST18952 7 DMA Controller The DMA controller manages data transfer between memories and external peripherals and has the following features: * * * four independent DMA channels transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces) cycle stealing operation: * * 3 cycles for a single data transfer (+1cycle for transfers on I space) (n+2) cycles for an n-data block transfer (+1cycle for transfers on I space) * each channel has: * * 3 signals: request (DMARQ), acknowledge (DMACK), interrupt request (DIT) 4x16 bit registers for block transfer facilities * fixed priority between the four channels (highest channel 0, lowest channel 3) The DMA controller DMARQ0-3 inputs and DMACK0-3 outputs are available as primary inputs, in the case of SIO inhibition. This is set by the DMAR register (see "DMAR: DMA management register" on page 44). Figure 7.1 IA ID XA XD DMA controller 16 AS-D SP YD YA 16 INTERR UPT D950Core 16 16 16 16 YRD YWR YBS CONTROLLER PERIPHERAL DMA_CLK 3 HOLD HOLDACK CLK INCY CLE DIT0 DIT1 DIT2 DIT3 DIT_AND RESET DMARQ0 DMARQ1 DMARQ2 DMARQ3 IRD IWR IBS XR D XW R XB S 3 3 DMA CONTROLLER PERIPHERAL DMACK0 DMACK1 DMACK2 DMACK3 DTACK DIP_ENA 21/66 ST18952 7.1 DMA operation The DMA controller interface contains four independent channels allowing data transfer on Imemory space and simultaneous data transfer on X and Y-memory spaces. When requests to transfer data on the same bus occur at the same time on different channels, the requests are concatenated to be acknowledged during the same transfer according to fixed priority. Channel 0 has the highest priority ranging to channel 3 with the lowest priority. The DMA transfer is based on a DSP cycle stealing operation: * * * DMA controller generates a `hold request'. The core sends back a `hold acknowledge' to the DMA controller and enters the hold state (bus released). The DMA controller manages the transfer and enters its idle state at the end of the transfer, until reception of a new DMA request. The `hold request' signal is removed. The data transfer duration is n+2 cycles, split into: * One cycle inserted at the beginning of the transfer when bus controls are released by the D950Core, n cycles for the number of data words to be transferred. Another cycle is inserted at the end of the transfer when bus controls are released by the DMA controller. * Single or block data can be transferred. The DMA request signal (DMARQ) can be either edge (single) or level (block) sensitive. Data blocks can be transferred one data at a time using an edge sensitive request signal. A double buffering mechanism is available to deal with data blocks requiring the allocation of 2N addresses for the transfer of an N data block. An interrupt can be used to warn AS-DSP that a predefined number of data have been transferred and are ready to be processed. Interrupt requests are sent from the DMA controller to the interrupt controller. The selected channels must be edge sensitive and the user has to define the proper priority. 22/66 ST18952 7.2 DMA registers Address registers Two 16-bit registers (unsigned) are dedicated per channel for address transfer: * * DIA: initial address. Contains the initial address of the selected address bus (see DBC-bit of DGC register). DCA: current address. Contains the value to be transferred to the selected address bus (see DBC-bit of DGC register) during the next transfer. The different DCA values are: DAI X 0 1 1 1 DLA X X 0 1 1 DCC = 0 X X X 0 1 DCA(n+1) 0 DCA(n) DCA(n) + 1 DCA(n) + 1 DIA Reset 1 0 0 0 0 Note: See "DAIC: Address/interrupt control register" on page 24 for DAI and DLA definitions Counting registers Two 16-bit registers (unsigned) per channel are dedicated for count transfer. For a transfer of an N data block, DIC and DCC registers have to be loaded with N-1. When DCC content is 0 (valid transfer count), it is loaded with DIC content for the next transfer. * * DIC: initial count. Contains the total number of transfers of the entire block DCC: current count. Contains the remaining number of transfers required to fill the entire block. It is decremented after each transfer. The DCC values are: Reset 1 0 0 DCC = 0 X 0 1 DCA(n+1) 0 DCA(n) - 1 DIC Control registers Three 16-bit control registers are dedicated to the DMA controller interface. These are the general control register, the address interrupt control register and the mask sensitivity control register. They are detailed below. 23/66 ST18952 DGC: General control register Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel 1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3). (Address = 0040, Reset = 0000h, Read/Write). 15 - 14 13 12 11 - 10 9 8 7 - 6 5 4 3 - 2 1 0 DRW3 DBC1 DBC0 DRW2 DBC1 DBC0 DRW1 DBC1 DBC0 DRW0 DBC1 DBC0 Bit Function DBC1/DBC0 Bus choice for data transfer 00: X-bus (default) 01: Y-bus 10: I-bus 11: reserved DRWi Data transfer direction 0: Write access (default) 1: Read access DAIC: Address/interrupt control register Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel 1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3). (Address = 0042, Reset = 0000h, Read/Write) 15 DAI3 14 DLA3 13 DIP3 12 DIE3 11 DAI2 10 DLA2 9 DIP2 8 DIE2 7 DAI1 6 DLA1 5 DIP1 4 DIE1 3 DAI0 2 1 0 DIE0 DLA0 DIP0 Bit DIEi Function Enable interrupt 0: Interrupt request output associated to channel i is masked (default) 1: Interrupt request output associated to channel i is not masked Interrupt pending 0: No pending interrupt on channel i (default) 1: Pending interrupt on channel i (enabled if DIP_ENA input is high) Load address 0: DCAi content incremented after each data transfer (default) 1: DCAi content loaded with DIA content if DCCi value is 0, or DCAi content incremented if DCCi value is not equal to 0 Address increment 0: DCAi content unchanged (default) 1: DCAi content modified according to DLAi state DIPi DLAi: DAIi 24/66 ST18952 DMS: Mask sensitivity control register Two bits are dedicated to each DMA channel (bits 0 and 1 to channel 0, bits 4 and 5 to channel 1, bits 8 and 9 to channel 2, bits 12 and 13 to channel 3). (Address = 0041, Reset = x3333h, Read/Write) 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 4 3 - 2 - 1 0 DSE3 DMK3 DSE2 DMK2 DSE1 DMK1 DSE0 DMK0 Bit DMKi Function DMA mask 0: DMA channel not masked 1: DMA channel masked (default) DMA sensitivity 0: Low level 1: Falling edge (default) DSEi 25/66 ST18952 8 Interrupt Controller The interrupt controller (ITC) can manage up to eight external interrupts. The interrupt controller has the following features: * 8 independent interrupt sources, each one associated with: * * * * * 16-bit programmable interrupt vector - provides the address of the first instruction of the interrupt routine associated with the source. mask bit, enabling each source to be activated or deactivated sensitivity bit (edge/level) 2-bit programmable priority level `pending interrupt' flag - displays the source waiting for service. This flag is writable to allow a software interrupt capability. * * Figure 8.1 Interrupt processing whenever its priority level is higher than the current priority level. Nested of up to 4 interrupts(the stack content is accessible in read or write). D950Core interrupt controller AS-DSP 16 YD YA 16 IT ITACK EOI D950Core YWR YRD IT ITACK EOI INTERRUPT ITRQ0 ITRQ1 ITRQ2 ITRQ3 ITRQ4 ITRQ5 ITRQ6 ITRQ7 YWR CONTROLLER YRD PERIPHERAL INCYCLE CLK RESET VR02020C The interrupt controller ITRQ inputs can be connected to external interrupt requests or to internal peripheral requests, this is dependent on the setting of the port/interrupt control (PICR) system register, see Table on page 43 for details. The interrupt controller receives interrupt 26/66 ST18952 requests from primary inputs P_ITRQ0-7 on its inputs ITRQ0-7 when bit 0-7 of the PICR register is set to `0'. Otherwise, the ITRQ0-7 input is connected to internal peripheral interrupt request output. Each input can be programmed independently. 8.1 Interrupt controller registers The interrupt controller interface is controlled by status and control registers mapped into the Y-memory space. Status registers are not write-protected. IVO0-7: Interrupt vector0-7 address registers The IVO0-7 registers (one per external interrupt) contain the first address of the interrupt routine and are associated with the respective interrupt input ITRQ0-7. The register content of the interrupt under service is provided on the YD bus during the cycle following the ITACK falling edge. (Address = 0020-0027, No reset value, Read/Write) 15 14 13 12 11 10 9 IVi 9 8 IVi 8 7 IVi 7 6 IVi 6 5 IVi 5 4 IVi 4 3 IVi 3 2 IVi 2 1 IVi 1 0 IVi 0 IVi 15 IVi 14 IVi 13 IVi 12 IVi 11 IVi 10 ICR: Interrupt control register The ICR register displays the current priority level and up to four stacked priority levels. (Address = 0028, Reset = 000Bh, Read/Write)) 15 14 SPL4 (2:0) 13 12 11 SPL3 (2:0) 10 9 8 SPL2 (2:0) 7 6 5 SPL1 (2:0) 4 3 ES 2 1 CPL (2:0) 0 Bit CPL ES Function Current priority level (-1, 0, 1, 2 or 3) (default is 011) Empty stack flag 0: stack is used 1: stack is not used (default) 3-bit 1st stacked priority level 3-bit 2nd stacked priority level 3-bit 3rd stacked priority level 3-bit 4th stacked priority level SPL1 SPL2 SPL3 SPL4 27/66 ST18952 The current priority levels available are shown in below. Priority level -1 0 1 2 3 Reserved Coding 111 000 001 010 011 100 - 110 Acceptable IT level priority 0,1,2,3 1,2,3 2,3 3 An interrupt request is acknowledged when its priority level (coded in the IPR register) is higher than the current priority level. In this case, the current priority level becomes the interrupt priority level and the previous current priority level is pushed onto the stack and displayed as stack priority level (SPL)1. The process is repeated over a range of four interrupt requests and the four previous current stack priority levels are displayed on SPL1, SPL2, SPL3 and SPL4. If less than four interrupts are pushed onto the stack, the unused SPL words are set to `000'. At the end of the interrupt routine, the priority levels are popped from the stack. The empty stack (ES) flag is used to indicate whether the stack is used or not. The ISP word of the ISP register indicates the depth of the stack (see below). Figure 8.2 ICR and ISPR Operation INTERRUPT LEVEL 2 INTERRUPT LEVEL 3 PROGRAM PROGRAM IT2 PROGRAM IT3 IT2 IT3 ICR SPL4 SPL3 SPL2 SPL1 ES CPL X ISPR X X X 1 -1 ISP 0 SPL4 SPL3 SPL2 SPL1 ES CPL X X X -1 0 2 ISP 1 SPL4 SPL3 SPL2 SPL1 ES CPL X X -1 2 0 3 ISP 2 28/66 ST18952 IMR: Interrupt mask/sensitivity register (Address = 0029, Reset = 5555h, Read/Write) 15 IS7 Bit IM 14 IM7 13 IS6 12 IM6 11 IS5 10 IM5 9 IS4 8 IM4 7 IS3 6 IM3 5 IS2 4 IM2 3 IS1 2 IM1 1 IS0 0 IM0 Function Interrupt mask 0: Interrupt is not masked 1: Interrupt is masked (default) Sensitivity 0: ITRQ is active on a low level (default) 1: ITRQ is active on a falling edge IS Each interrupt input ITRQ0-7 can be masked individually when the corresponding IM0-7 bit is set. In this case any activity on the ITRQ0-7 pin is ignored. All IM bits are set during DSP reset. ITRQ0-7 is active either on a low level when IS0-7 is low (by default on reset) or on a falling edge when IS0-7 is high. When ITRQ0-7 is active on a low level, it must stay low until the ITACK falling edge is sampled. IPR: Interrupt priority register (Address = 002A, Reset = 0000h, Read/Write)) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP7(1:0) Bit IP IP6(1:0) Function Interrupt priority level (0, 1, 2 or 3) (default is 0) IP5(1:0) IP4(1:0) IP3(1:0) IP2(1:0) IP1(1:0) IP0(1:0) The IPR register contains the priority level of each ITRQ0-7 interrupt input. IP0-7 priority level is coded using two bits. The different values of IP are 0, 1, 2, 3 (0 lowest priority, 3 highest priority). When two ITRQ with the same priority level are requesting during the same cycle, the first acknowledged interrupt is the one corresponding to the lowest number (for example, ITRQ0 acknowledged prior to ITRQ3). 29/66 ST18952 ISPR: Interrupt stack pointer register (Address = 002B, Reset = 0000h, Read/Write) 15 Bit ISPR Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ISP(2:0) 0 Function Number of stacked priority levels (0, 1, 2 or 3) '-' is RESERVED (read: 0, write: don't care) ISPR contains the number of stacked priority levels. If the ISPR value is directly written, the SPLi/CPL values are modified. So the ICR register content is no longer significant but the interrupt routine procedure is not affected. After reset, ISPR default value is 0 ISR: Interrupt status register (Address = 002C, Reset = 0000h, Read/Write) 15 Bit IPE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPE7 IPE6 IPE5 IPE4 IPE3 IPE2 IPE1 IPE0 Function Interrupt pending bit 0: Reset when interrupt request is acknowledged (default) 1: Set when interrupt request is recorded `-' is RESERVED (read: 0, write: don't care) Note: An interrupt pending (IPE) bit is associated with each interrupt input. IPE is set when the interrupt request is recorded and is reset when the interrupt request is acknowledged (ITACK falling edge). When the user does not want to acknowledge any of the pending interrupt requests, the IPE flag of the CCR register must first be reset and then the ISR register set to "0000". When only some pending interrupt requests need to be acknowledged, the IPE bits of the other interrupt inputs must be reset. When the IPE bit is set by a direct register write an interrupt request will be generated irrespective of the state of the ITRQ pin. When the mask (IM) bit is set, the corresponding IPE bit is reset. 30/66 ST18952 9 Timers There are two timer (TIM) units on the ST18952. The timers enable interrupts to be generated after predefined periods of time. Each timer has the following features: * * * * * * 16 bits linear timer / 4 bits exponential prescaler counting between 16 bits "start value" and 16 bits "end value" counting period between 2 cycles and 232 cycles (50ns to 107s for a 40 MHz D950). Note, 1 cycle = 2 MCLK periods. 1 maskable interrupt request external counting clock input programmable functions: * * * * external / internal clock up / down counting continue / stop modes interrupt enable When bit 4 of the PICR system register (see Table ) is set to `1', TIM0 interrupt request output is connected to the ITRQ4 input of the interrupt controller. When bit 5 of the PICR register is set to `1', TIM1 interrupt request output is connected to the ITRQ5 input of the interrupt controller. Refer to Chapter 8 for full details on the interrupt controller. After reset, the timers interrupt outputs are not connected. Setting the timer enable (TEN) bit of the timer control (TCR) register to `1' starts the timer. 9.1 Timer registers TCR0-1: Timer control register The timer control register (TCR) contains timer control information. (Address = 0058/005C, Reset value = 0000 h, Read/Write) 15 (0) Bit TEN 14 (0) 13 (0) 12 (0) 11 (0) 10 (0) 9 8 7 6 5 4 3 2 1 0 TFP(3:0) ITCM TIE TCS TLE TUD TEN Function Timer enable (bit 0) * When TEN = `0', the TIM is disabled. * When TEN = `1', the TIM is started. Note: the timer must be disabled before the timer registers are configured, otherwise its behavior is not guaranteed. Once configured it can be enabled. 31/66 ST18952 TUD TLE Timer up/down counting (bit 1) * When TUD = `0', the TIM is counting `down' (reset value), i.e. the TCVR current value register content is decremented. * When TUD = `1', the TIM is counting `up', i.e. the TCVR current value register content is incremented. Timer load enable (bit 2) * When the counter has reached its end value (TCVR = TEVR), TCVR is (re)loaded with TSVR (`start value') register content when TLE = `1'. * When TLE = `0' (reset value), the next state of TCVR depends on the TCS bit. Timer continue/stop (bit 3) * When TLE = `0' (no load) and when the counter has reached its end value (TCVR = TEVR), the TCVR content continues to increment/decrement according to TUD bit when TCS = `1' (continue mode). * When TCS = `0' (stop mode - reset value), TCVR is stopped and content is frozen. Timer interrupt enable (bit 4) * When the counter has reached its end value (TCVR = TEVR), an interrupt request is generated on TIR output when TIE = `1'. * When TIE = `0' (reset value), TIR output is disabled (=`1'). Timer cock mode (bit 5) * When TCM = `0' (reset value), the TCVR clock is derived from internal MCLK clock according to TFP bits. * When TCM = `1', the TCVR clock is the external ECLK clock. Timer frequency prescaler (bits 9-4; TFP(3) = msb) * When TCM = `0' (internal clock), the TCVR register clock is derived from the MCLK clock input by dividing MCLK by 2(2+ TFP). The coding is as follows: TFP = 0h prescaler by 2 (reset value) MCLK divided by 4 TFP = 1h prescaler by 4 MCLK divided by 8 TFP = 2h prescaler by 8 MCLK divided by 16 -... TFP = Fh prescaler by 216MCLK divided by 217 RESERVED and must be written as'0' Unused and read as'0' TCS TIE TCM TFP(3:0) Bits 10-11 Bits 12-15 TSVR0-1: Timer start value register (Address = 0059/005D, Reset value = 0000 h, Read/Write) 15 TSV 15 14 TSV 14 13 TSV 13 12 TSV 12 11 TSV 11 10 TSV 10 9 TSV 9 8 TSV 8 7 TSV 7 6 TSV 6 5 TSV 5 4 TSV 4 3 TSV 3 2 TSV 2 1 TSV 1 0 TSV 0 Bit TSV(15:0) Function Timer start value (bits15-0, TSV15 is msb 32/66 ST18952 TSVR contains the data to be transferred to the TCVR current value register when: 1: TEN = `1' (TIM enable) TLE = `1' (TIM load enable) TCVR = TEVR (count period finished) TCS = `1' (stop mode disabled). 2: First counting clock rising edge after timer start (timer starts on rising edge of TEN ).??? TEVR0-1: Timer end value register (Address = 005A/005E, Reset value = 0000 h, Read/Write)) 15 TEV 15 14 TEV 14 13 TEV 13 12 TEV 12 11 TEV 11 10 TEV 10 9 TEV 9 8 TEV 8 7 TEV 7 6 TEV 6 5 TEV 5 4 TEV 4 3 TEV 3 2 TEV 2 1 TEV 1 0 TEV 0 Bit TEV(15:0) Function Timer end value (bits15-0 - TEV(15) = msb TEVR contains the data to be compared to the TCVR current value register. TCVR0-1: Timer current value register (Address = 005B/005F, Reset value = 0000 h, Read only) 15 TCV 15 14 TCV 14 13 TCV 13 12 TCV 12 11 TCV 11 10 TCV 10 9 TCV 9 8 TCV 8 7 TCV 7 6 TCV 6 5 TCV 5 4 TCV 4 3 TCV 3 2 TCV 2 1 TCV 1 0 TCV 0 Bit TCV(15:0) Function Timer current value (bits15-0 - TCV(15) = msb) TCVR contains the current counting value. When TCVR = TEVR, the TCVR content is changed according to Table 9.1. The TCVR clock is derived from internal MCLK clock according to TFP bits when TCM = `0' or is equal to external ECLK clock when TCM = `1'. Note: Timers external clocks are not directly user accessible. They are connected to INCYCLE. 33/66 ST18952 Table 9.1 TLE x x x 0 x 0 1 Counting modes TCS x 0 x 1 x 1 1 TCVR(n) = TEVR x 1 0 1 0 1 1 TUD x x 0 1 x TEN 0 1 TCVR(n+1) TCVR(n) TCVR(n)-1 TCVR(n)+1 TSVR Description TIM disable stop decrement decrement (continue) increment increment (continue) load 34/66 ST18952 10 SIO The ST18952 has two synchronous serial input/output (SIO) ports which link to serial devices such as codecs and to other processors. The SIO ports work in DMA mode. SIO0 uses channels 0 and 1 of the DMA controller, SIO1 uses channels 2 and 3. The chip must be configured for SIO using the DMAR system register ("DMAR: DMA management register" on page 44). For SIO port 0, bits 1 and 0 of the DMAR register must be reset to inhibit external DMA requests (1 and 0) and to allow SIO port 0 communication with the outside. For SIO port 1, bits 3 and 2 of the DMAR register must be reset to inhibit external DMA requests (3 and 2) and to allow SIO port 1 communication with the outside. The SIO ports have the following features: * * * double-buffered full-duplex operation frequency up to D950 input clock (33 Mbps for 66 MHz D950) programmable functions * * * * * word length: 8/16 bits (msb first) up to 8 words per frame frequency prescaler (by 1 or 3) and divider (by 21 to 28) synchronization signal: bit length/word length, delayed/not delayed, active level clock signal: internal/external, active edge * * 4 status flags / 2 enabled interrupt requests data transfers between SIO and memories using DMA 35/66 ST18952 10.1 SIO registers Each SIO port has the following set of registers. STB0-3: SIO transmit buffers STB0-3 buffers contain the data to be transferred to the SIO transmit shift register. SIO0 registers * * * * * * * * (STB0: Address = 0068h, reset value = 0000 h, write only) (STB1: Address = 0069h, reset value = 0000 h, write only) (STB2: Address = 006Ah, reset value = 0000 h, write only) (STB3: Address = 006Bh, reset value = 0000 h, write only) SIO1 registers (STB0: Address = 00E8 h, reset value = 0000 h, write only) (STB1: Address = 00E9 h, reset value = 0000 h, write only) (STB2: Address = 00EA h, reset value = 0000 h, write only) (STB3: Address = 00EB h, reset value = 0000 h, write only) SRB0-3: SIO receive buffers SRB0-3 buffers contain the data transferred from the SIO receive shift register. SIO0 registers * * * * * * * * (SRB0: Address = 006Ch, reset value = xxxx h, read only) (SRB1: Address = 006Dh, reset value = xxxx h, read only) (SRB2: Address = 006Eh, reset value = xxxx h, read only) (SRB3: Address = 006Fh, reset value = xxxx h, read only) SIO1 registers (SRB0: Address = 00EC h, reset value = xxxx h, read only) (SRB1: Address = 00ED h, reset value = xxxx h, read only) (SRB2: Address = 00EE h, reset value = xxxx h, read only) (SRB3: Address = 00EF h, reset value = xxxx h, read only) 36/66 ST18952 SCOR: SIO sequence control register (SIO0 Address = 0070h, reset value = 0000h, read/write) (SIO1 Address = 00F0 h, reset value = 0000h, read/write) 15 14 13 12 11 10 9 (0) 8 7 6 5 4 3 2 1 0 SEQ(1:0) Bit SEQ(1:0) Function Four SIO sequences (defining the time slots order) are available: SEQ=00 Data/Data/Data/Data SEQ=01 Data/Control/Data/Control SEQ=10 Data/Data/Control/Control SEQ=11 Control/Control/Control/Control Data time slots are transferred using the DMA controller, and control time slots are transferred using SIO buffers. Unused and read as `0' Bits 2-15 SCR: SIO control register (SIO0 address = 0062h, reset value = 0000h, read/write) (SIO1 address = 00E2h, reset value = 0000h, read/write) 15 (0) 00 14 13 SLL 0 12 0 11 1 10 STIE 1 9 8 SWN(2:0) 011 7 6 0 5 0 4 SSL 0 3 SCE 0 2 SCSD 0 1 SWL 0 0 SMS 0 SMEN SRIE SSM SSAL Bit SMS SWL Function SIO Mode select: Must be set to 0 (normal mode) SIO Word length SWL = `0' Word length is 16 bits (reset value) SWL = `1' Word length is 8 bits SIO Clock/synchro direction Determines whether SCK clock and SFS frame synchro signals are generated externally or internally SCSD = `0' Generated externally (reset value) SCSD = `1' Generated internally SIO Clock edge SCE = `0' SCE = `1' SCK rising edge active (reset value) SCK falling edge active SCSD SCE SSL SIO Frame syncro length Generated in a bit-length manner (active for one clock cycle) when SSL='0' (reset value) or in a word-length manner (active for 8 or 16 clock cycles dep. on SWL bit) when SSL='1'. SIO Frame synchro active level SSAL = `0' SFS high level active (reset value) SSAL = `1' SFS low level active SSAL 37/66 ST18952 Bit SMS SSM Function SIO Mode select: Must be set to 0 (normal mode) SIO Frame synchro mode The SFS frame synchro is generated one clock cycle before the first data of the frame (delayed mode) when SSM = `0' (reset value) or when first data is transmitted/received (non-delayed mode) when SSM = `1'. SIO word number (SWN(2) = msb) SWN determines the number of words inserted in the frame (up to 8). The coding is as follows: SWN = "0" -> 1 time slot SWN = "1" -> 2 time slots ... SWN = "7" -> 8 time slots The reset value is SWN = "0" SIO Transmit interrupt enable * When STIE = `1', interrupt request generated on the STI output when STDE flag = `1'. * When STIE = `0' (reset value), the STI output is disabled (`1') SIO Receive interrupt enable * When SRIE = `1', interrupt request generated on SRI output when the SRDF flag = `1'. * When SRIE = `0' (reset value), the SRI output is disabled (`1') SIO Microwire enable: Must be set to 0 (normal mode) SIO Local loop * When SLL = `1', the STD output is internally linked to the SRD input. This allows the SIO behavior to be checked without providing data on the SRD input. * When SLL = `0' (reset value), the SRD input is enabled Unused and are read as `0' SWN(2:0) STIE SRIE SMEM SLL Bits 15-14 SCR writes must be made when the SIO is disabled (SEN bit of the SIO enable register is `0')SMS: 38/66 ST18952 SFR: SIO Frequency register (SIO0 address = 0063h, reset value = 0000h, read/write) (SIO1 address = 00E3 h, reset value = 0000h, read/write) SFR Writes must be made when the SEN bit of the SER register is `0' (SIO disabled) 15 14 13 12 11 (0) 10 9 8 7 6 5 0 4 3 2 SFD(2:0) 1 0 SFP Bit SFP Function SIO Frequency prescaler * When the SCK clock is generated internally (SCSD bit of the SCR register is set to `1'), it is derived from the MCLK clock input by first prescaling MCLK by 1 (SFP = `0' reset value) or by 3 (SFP = `1'). SIO Frequency divider (bits 3-1; SFD(2) = msb) * When the SCK clock is generated internally (SCR/SCSD = `1'), it is derived from the MCLK clock input by second dividing MCLK by 2(1 + SFD). SFD = "0" divided by 2 (reset value) SFD = "1" divided by 4 SFD = "2" divided by 8 ... SFD = "7" divided by 256 Reserved and must be written as `0' Unused and read as `0' SFD(2:0) Bits 5 and 4 Bits 15 to 6 SER: SIO Enable register (SIO0 address = 0064h, reset value = 0000h, read/write) (SIO1 address = 00E4 h, reset value = 0000h, read/write) 15 14 13 12 11 10 9 8 (0) 7 6 5 4 3 2 1 0 SEN Bit SEN Bits 15 to 1 Function SIO Enable * When SEN = `0', SIO is disabled (reset value). SCR and SFR writes must be made when SEN = `0'. * When SEN = `1', the SIO is enabled. Unused and read as `0' 39/66 ST18952 SSR: SIO Status register (SIO0 address = 0065h, reset value = 0000 h, read only) (SIO1 address = 00E5h, reset value = 0000 h, read only) 15 14 13 12 11 10 9 8 7 6 SCWN(2:0) 5 4 0 3 2 1 0 SLRA(7:0) SROV SRDF STUN STDE Bit STDE Function SIO Transmit data empty * STDE is set when the content of the STDR Data register is transferred into the Transmit Shift register signalling that the STDR Data register is ready to be receive the next word to be transmitted. * If the STIE enable bit is set, an interrupt request occurs on the STI output (STI is low for 1 MCLK cycle) when STDE is set. SIO Transmit underrun * STUN is set when the Transmit Shift register is empty and the STDR Data register has not been filled by the DSP. * If another frame syncho occurs, the content of the STDR Data register is transferred again into the Transmit Shift register and the previous word is re-transmitted. SIO Receive data full * SRDF is set when the content of the Receive Shift register has been transferred into the SRDR Data register, signalling a new word receive. The SRDR Data register is ready to be read by the DSP. * If the SRIE enable bit is set, an interrupt request occurs on the SRI output (SRI is low for 1 MCLK cycle) when SRDF is set. SIO Receive overrun * SROV is set when the Receive Shift register is ready to be transferred into the SRDR Data register, which has not been read by the DSP. * If another frame syncho occurs, the content of the Receive Shift register is transferred into the SRDR Data register and the previous content of SRDR is lost. Unused and read as `0' SIO Current word number (SCWN(2) = msb) * In normal and microwire modes, SCWN contains the current word number value since the last frame synchro. In tdm mode, SCWN determines the current slot number value since the last frame synchro. SCWN = 0 -> 1st sub-frame / time slot SCWN = 1 -> 2nd sub-frame / time slot ... SCWN = 7 -> 8th sub-frame / time slot SIO Last received address (bits 15-8) Must write 0. STUN SRDF SROV Bit 4 SCWN(2:0) SLRA(7:0) 40/66 ST18952 STDR: SIO Transmit data register (SIO0 address = 0060h reset value = 0000h, write only) (SIO1 address = 00E0h reset value = 0000h, write only) 15 STD 15 14 STD 14 13 STD 13 12 STD 12 11 STD 11 10 STD 10 9 STD 9 8 STD 8 7 STD 7 6 STD 6 5 STD 5 4 STD 4 3 STD 3 2 STD 2 1 STD 1 0 STD 0 Bit STD(15:0) Function SIO Transmit data (STD(15) = msb) * STD contains the data to be transferred to the Transmit Shift register at the beginning of the next sub-frame or time slot. The data is transmitted msb first. * When 8-bit data format (SCR/SWL = `1') is used, the byte must be left justified (written on bits 7 to 0, bits 15 to 8 are ignored). The msb is bit 7. SRDR: SIO Receive data register (SIO0 address = 0061h, reset value = xxxxh, read only) (SIO1 address = 00E1h, reset value = xxxxh, read only) 15 SRD 15 14 SRD 14 13 SRD 13 12 SRD 12 11 SRD 11 10 SRD 10 9 SRD 9 8 SRD 8 7 SRD 7 6 SRD 6 5 SRD 5 4 SRD 4 3 SRD 3 2 SRD 2 1 SRD 1 0 SRD 0 Bit SRD(15:0) Function SIO Receive data (SRD(15) = msb) * SRD contains the data transferred from the Receive Shift register at the end of the last sub-frame or time slot. The data is right justified (msb = bit 15). * When 8-bit data format (SCR/SWL = `1') is used, the byte is left justified (significative on bits 7 to 0, bits 15 to 8 are ignored). The msb is bit 7. 41/66 ST18952 11 External Coprocessor Dedicated co-processors can be designed by SGS-Thomson, by customer request. The D950Core instruction set includes two co-processor dedicated one-word instructions, allowing one (COPS) or two (COPD) parallel data moves between X or Y-memory space and co-processor registers. While a co-processor instruction is decoded by the D950Core, the VCI output is asserted high, indicating to the co-processor that such an instruction will be executed at the next cycle. Control and status registers, at least one of each, must be included in the co-processor. This allows initialization in various operating modes and gives information to the D950Core on operations in progress and status. An external coprocessor can only be used when program and data bus extensions are enabled. 12 System Control System control is provided by glue logic and performs the following functions: * * * * * * Control of bus extensions and multiplexing of BSU and X extension IO's. Interrupt vector management (in case of interrupt controller inhibition) Control of input clock frequency Test control management Bus requests (Hold) arbitration Buffering 42/66 ST18952 12.1 System registers There are 4 system registers: CMR clock management register; PICR port/interrupt control register; INTR interrupt vector register; and DMAR DMA management register. The registers are Y memory-mapped. PICR: Port/interrupt control register The interrupt controller ITRQ inputs can be connected to external interrupt requests or to internal peripheral requests, this is dependent on the setting of the port/interrupt control (PICR) system register. The interrupt controller receives interrupt requests from primary inputs P_ITRQ0-7 on its inputs ITRQ0-7 when bit 0-7 of the PICR register is set to `0'. Otherwise, the ITRQ0-7 input is connected to the internal peripheral interrupt request output. Each input can be programmed independently. (Address = 0049 h, Reset value = 0000 h, Read/Write) 15 14 13 12 11 10 9 8 NM Bit DMA0 DMA1 DMA2 DMA3 TIM0 TIM1 IO IO NM Function 0: ITC ITRQ0 connected to P_ITRQ0 primary I/O 1: ITC ITRQ0 connected to DMA DIT0 output 0: ITC ITRQ1 connected to P_ITRQ1 primary I/O 1: ITC ITRQ1 connected to DMA DIT1 output 0: 1: 0: 1: 0: 1: ITC ITRQ2 connected to P_ITRQ2 primary I/O ITC ITRQ2 connected to DMA DIT2 output ITC ITRQ3 connected to P_ITRQ3 primary I/O ITC ITRQ3 connected to DMA DIT3 output ITC ITRQ4 connected to P_ITRQ4 primary I/O ITC ITRQ4 connected to TIMER0 interrupt request output 7 IO 6 IO 5 4 3 2 1 0 TIM1 TIM0 DMA3 DMA2 DMA1 DMA0 0: ITC ITRQ5 connected to P_ITRQ5 primary I/O 1: ITC ITRQ5 connected to TIMER1 interrupt request output 0: ITC ITRQ6 connected to P_ITRQ6 primary I/O 1: ITC ITRQ6 is not used (connected to VDD) 0: ITC ITRQ7 connected to P_ITRQ7 primary I/O 1: ITC ITRQ7 is not used (connected to VDD) 0: Normal mode. 1: ITC inhibited (bit 7-0 UNUSED). D950Core IT input directly connected to P_ITRQ-7 primary I/O. UNUSED Bits15:9 Note: P_ITRQ0-7 primary I/Os are used for external interrupt requests and for the D950 8-bit general purpose parallel port (P0-7). Depending on the PICR value and the programming of 43/66 ST18952 the D950 parallel port (input or output), the interrupt controller can be fed by the D950 parallel port output. INTR: Interrupt vector register (Address = 004Ah, Reset = 0000h, Write only) In the case of the interrupt controller being inhibited (bit 8 of the PICR register set to `1'), the INTR register controls interrupt vector generation. This register must be initialized (INTR=0000 after reset) and can not be read. After reset, ITC inputs are fed with external interrupt requests. DMAR: DMA management register The DMA controller DMARQ0-3 inputs and DMACK0-3 outputs are available as primary inputs, in case of SIO inhibition. This is set by the system register DMAR. (Address: 004Bh, Reset = 0000h, Read/Write): 15 14 13 12 11 10 9 8 7 6 5 4 3 D3 Function 0: DMARQ0 connected to DMARQ0 SIO0 and DMACK0 connected to DMACK0 1: DMARQ0 connected to external DMARQ0 input called (DMARQ0_SRD0) and DMACK0 connected to external DMACK0 input called (DMACK0_STD0) 0: DMARQ1 connected to DMARQ1 SIO0 and DMACK1 connected to DMACK1 1: DMARQ1 connected to external DMARQ1 input called (DMARQ1_SCK0) and DMACK1 connected to external DMACK1 input called (DMACK1_SFS0) 0: DMARQ2 connected to DMARQ0 SIO1 and DMACK2 connected to DMACK0 1: DMARQ2 connected to external DMARQ2 input called (DMARQ2_SRD1) and DMACK2 connected to external DMACK2 input called (DMACK2_STD1) 0: DMARQ3 connected to DMARQ1 SIO1 and DMACK3 connected to DMACK1 1: DMARQ3 connected to external DMARQ3 input called (DMARQ3_SCK1) and DMACK3 connected to external DMACK3 input called (DMACK3_SFS1) Not used SIO0 2 D2 1 D1 0 D0 Not used Bit D0 D1 SIO0 D2 SIO1 D3 SIO1 Bit 4 - 15 Outputs DIT0-3 are connected to the interrupt controller inputs ITRQ0-3 (via PICR system register described above). HOLD DMA output is connected to HOLD D950 input through an arbitration module, which takes into account external HOLD requests and manages HOLDACK generation to the right HOLD sender. After reset, DMA requests come from the SIO. 44/66 ST18952 Note: Use of an external DMA controller is possible. In this case, only exchanges between external peripherals and external memories are allowed. All direct extension buses are isolated. 12.2 Clocks A 27 MHz crystal can be used with the on-chip oscillator and PLL to provide the D950 clock input. The PLL module multiplies the oscillator frequency by a factor of 10 and generates a 270 MHz signal. A programmable divisor is connected to the PLL output to generate the D950 clock input. The division range is 2 to 256 and can be programmed by writing to the CMR clock management system register. CMR: Clock management register (Address = 0048h, Reset = 0000h, Read/Write) 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 D2 1 D1 0 D0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Division factor 2 4 8 16 32 64 128 256 Output clock frequency 135 MHz 67.5 MHz 33.74 MHz 16.88 MHz 8.44 MHz 4.22 MHz 2.11 MHz 1.05 MHz The oscillator and PLL can be bypassed by setting the CLK_MODE pin to `1'. In this case the D950 CLKIN input receives the clock signal directly from the MCLK input. 45/66 ST18952 13 JTAG IEEE 1149.1 test access port The Test Access Port (TAP) conforms to IEEE standard 1149.1. The TAP consists of five pins: TMS, TCK, TDI, TDO and TRST. TDO can be overdriven to the power rails, and TCK can be stopped in either logic state. The instruction register is 8 bits long, with no parity, and the pattern "00000001" is loaded into the register during the Capture-IR state. There are three defined public instructions, see Table 13.1. All other instruction codes are reserved. Table 13.1 Instruction codes Instruction IDCODE EMU BYPASS Selected register Identification D950 IOscan Bypass 04h 08h FFh Notes 1: MSB... LSB; LSB closest to TDO Instruction code1) 14 Emulation Unit The emulation unit (EMU) performs to emulation and test fuctions through the external IEEE 1149.1 JTAG interface. Refer to "JTAG IEEE 1149.1 test access port" on page 46. The emulation and test operations are controlled by the JTAG Test Access Port (TAP) and the emulator by means of dedicated control I/Os. Emulation mode can entered in one of two ways: * * Asserting ERQ input pin low. Meeting a valid breakpoint condition or executing an instruction in single step mode. The PC board emulator is able to display the processor status (memories and registers) and restore the context. The Emulation resources (see Figure 14.1) include: * * * * Four breakpoint registers (BP0, BP1, BP2, BP3) which can be affected by Program or Data memory. Breakpoint counter (BPC). Program Counter Trace Buffer (PCB) able to store the address of the 6 last executed instructions. Three control registers for Breakpoint condition programming. 46/66 ST18952 * Figure 14.1 Control logic for instruction execution through the PC-board emulator control. Emulation block diagram BP registers Comparators IA XA / YA XD / YD IA RD/WR D950 TAP Control Registers Control Logic PC trace ERQ, IDLE, SNAP The emulation controller interface (see Table 2.8 and Table 2.9 on page 8) include pins of different types: * * * ERQ, IDLE and SNAP are used by the emulator tools. HALTACK indicates that the processor is halted in emulation mode. AIEBP, AXEBP and AYEBP may be used to set additional conditions for breakpoint validation on the respective IA/XA/YA buses. 47/66 ST18952 15 Electrical Specifications In the following tables TBD indicates `to be defined'. 15.1 DC Absolute maximum ratings Table 15.1 Symbol VDD VIN TA TSTG DC absolute maximum ratings Parameter Supply Voltage Input Voltage Operating Junction Temperature Range Storage Temperature Range Value -0.3 / 3.9 -0.3 / 3.9 -40 / +125 -55 / +150 Unit V V oC oC 15.2 DC Electrical characteristics Junction temperature: -40oC to +125oC Table 15.2 Symbol VDD VIL VIH VOL VOH IDD ISB DC electrical characteristics Parameter Power supply Input low level Input high level Output low level Output high level Operating Current Stand-by Current 0.85*VDD TBD TBD Min 2.7 0.8*VDD 0.4 Typical 3.3 Max 3.6 0.3*VDD Unit V V V V V mA A 48/66 ST18952 15.3 AC Characteristics The following timings are based on simulations and may change when full characterisation is completed. Clocks electrical characteristics Figure 15.1 Clock timing diagram t0 MCLK t3 t4 CLKOUT t5 t6 INCYCLE Table 15.3 No t0 t3 t4 t5 t6 Clock timing data Parameter Master clock cycle time CLKOUT high delay CLKOUT low delay INCYCLE high delay INCYCLE low delay Min (ns) Typ (ns) 7.5 4.0 3.3 -0.1 -0.5 Max (ns) 49/66 ST18952 Reset electrical characteristics Figure 15.2 Reset timing diagrams t0 MCLK CLKOUT t7 X RESET t8 RESET_OUT X t0 MCLK CLKOUT RESET RESET_OUT t9 t10 Table 15.4 No t0 t7 t8 t9 t10 Reset timing data Parameter Master clock cycle time RESET low setup RESET_OUT low delay RESET high setup RESET_OUT high delay Min (ns) Typ (ns) 7.5 2.4 1.7 nc 1.9 Max (ns) 50/66 ST18952 Bus control electrical characteristics Figure 15.3 Bus control timing diagram t0 MCLK CLKOUT INCYCLE t13 t11 t12 DTACK 51/66 ST18952 Table 15.5 No t0 t11 t12 t13 Bus control timing data Parameter Master clock cycle time DTACK high setup DTACK low setup DTACK high hold Min (ns) Typ (ns) 7.5 t0/4 t0/4 0 Max (ns) Control I/O electrical characteristics Figure 15.4 Control I/O timing diagram t0 MCLK CLKOUT CONTROL_IN CONTROL_OUT t14 t15 Table 15.6 No t0 t14 t15 Control I/O timing diagram Min (ns) Typ (ns) 7.5 6.0 3.0 Max (ns) Parameter Master clock cycle time CONTROL_IN setup CONTROL_OUT high/low delay 52/66 ST18952 Instruction bus electrical characteristics Figure 15.5 Instruction bus timing diagram t0 MCLK INCYCLE CLKOUT t27 t28 IAE t29 X t30 X IBSE t31 t32 t33 IDE t34 X t35 t37 t36 IWRE X t38 t39 IDE IRDE Table 15.7 No t0 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 Instruction bus timing data Parameter Master clock cycle time IAE valid delay IAE hold time IBSE low delay IBSE high delay IDE high to lo Z delay IDE valid delay IDE hold time IWRE low delay IWRE high delay IDE setup IDE hold IRDE low delay IRDE high delay Min (ns) Typ (ns) 7.5 1.9 1.1 0.3 0.0 tbd tbd 1.2 t0/2 + 1.6 0.6 5.8 -4.5 t0/2 + 0.5 0.6 Max (ns) 53/66 ST18952 X-data bus electrical characteristics Figure 15.6 X-data bus timing diagram t0 MCLK INCYCLE CLKOUT t40 t41 EA_XAE t42 X t43 X XBSE t44 t45 t46 ED_XDE t47 X t48 t50 t49 XWRE_EXWR X t51 t52 ED_XDE XRDE_EXRD Table 15.8 No t0 t40 t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 X-data bus timing data Parameter Master clock cycle time EA_XAE valid delay EA_XAE hold time XBSE low delay XBSE high delay ED_XDE high to low Z delay ED_XDE valid delay ED_XDE hold time XWRE_EXWR low delay XWRE_EXWR high delay ED_XDE setup ED_XDE hold XRDE_EXRD low delay XRDE_EXRD high delay Min (ns) Typ (ns) 7.5 t0+3.7 2.7 0.1 -0.2 tbd t0+3.9 0.3 t0+2.7 0.4 6.5 -5.0 t0+2.6 -0.7 Max (ns) 54/66 ST18952 Y-data bus electrical characteristics Figure 15.7 Y-data bus timing diagram t0 MCLK INCYCLE CLKOUT t53 t54 YAE_SA t55 X t56 X YBSE t57 t58 t59 YDE_SD t60 X t61 t63 t62 YWRE X t64 t65 YDE_SD YRDE Table 15.9 No t0 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 t65 Y-data bus timing data Parameter Master clock cycle time YAE_SA valid delay YAE_SA hold time YBSE low delay YBSE high delay YDE_SD high to lo Z delay YDE_SD valid delay YDE_SD hold time YWRE low delay YWRE high delay YDE_SD setup YDE_SD hold YRDE low delay YRDE high delay MIN (ns) Typ (ns) 7.5 3.5 2.6 0.1 0.3 tbd t0+3.5 0.5 t0+1.7 0.5 7.9 -5.2 t0+1.2 0.6 Max (ns) 55/66 ST18952 Bus switch electrical characteristics (Intel mode) Figure 15.8 Bus switch timing diagram (intel mode) t0 MCLK INCYCLE CLKOUT EA_XAE t69 t68 t67 t66 X t70 X ED_XDE t71 X Data_out t72 EI/X/YWR t74 t73 ED_XDE t75 X t76 EI/X/YRD Table 15.10 Y-data bus switch timing data No t0 t66 t67 t68 t69 t70 t71 t72 t73 t74 t75 t76 Parameter Master clock cycle time EA_XAE valid delay EA_XAE hold time ED_XDE high to lo Z delay ED_XDE valid delay ED_XDE hold time EI/X/YWR low delay EI/X/YWR high delay ED_XDE setup ED_XDE hold EI/X/YRD low delay EI/X/YRD high delay Min (ns) Typ (ns) 7.5 4.4 3.3 tbd t0+2.4 1.6 t0+2.3 1.9 7.1 -5.8 t0+2.1 -1.5 Max (ns) 56/66 ST18952 16 Y SPACE Memory Mapping 16.1 Memory map Figure 16.1 RESERVED External Y memory space Internal Y dual port RAM Internal Y RAM RESERVED Serial input/output1 RESERVED Serial input/output 0 Timer1 Timer0 RESERVED Bus switch unit RESERVED System control RESERVED DMA controller RESERVED Interrupt controller RESERVED Emulator peripheral RESERVED D950Core ST18952 memory map FFFF-FFD3 FFD2-3000 21FF-2000 1FFF-1000 00FF-00F1 00F0-00E0 00DF-0071 0070-0060 005F-005C 005B-0058 0057-0056 0055-0050 004F-004C 004B-0048 0047-0043 0042-0030 002F-002D 002C-0020 001F-0019 0018-0010 000F-0008 0007-0000 16.2 Serial input/output registers Table 16.1 Address (Hex) 00F1-00FF 00F0 00EF 00EE 00ED 00EC 00EB SCOR SRB3 SRB2 SRB1 SRB0 STB3 SIO1 registers Register Description reserved SIO control register SIO receive buffer SIO receive buffer SIO receive buffer SIO receive buffer SIO transmit buffer 57/66 ST18952 00EA 00E9 00E8 00E7 00E6 00E5 00E4 00E3 00E2 00E1 00E0 STB2 STB1 STB0 -/-/STSR -/SAR/SMR SSR SER SFR SCR SRDR STDR SIO transmit buffer SIO transmit buffer SIO transmit buffer reserved - unused on the ST18952 reserved - unused on the ST18952 Status Enable Frequency Control Receive data Transmit data Table 16.2 Address (Hex) 0071-00DF 0070 006F 006E 006D 006C 006B 006A 0069 0068 0067 0066 0065 0064 0063 0062 0061 0060 SIO0 registers Register SCOR SRB3 SRB2 SRB1 SRB0 STB3 STB2 STB1 STB0 -/-/STSR -/SAR/SMR SSR SER SFR SCR SRDR STDR Description reserved SIO control register SIO receive buffer SIO receive buffer SIO receive buffer SIO receive buffer SIO transmit buffer SIO transmit buffer SIO transmit buffer SIO transmit buffer reserved - unused on the ST18952 reserved - unused on the ST18952 Status Enable Frequency Control Receive data Transmit data 58/66 ST18952 16.3 Timer registers Table 16.3 Address (Hex) 005F 005E 005D 005C Timer1 registers Register TCVR TEVR TSVR TCR Description Timer current value register 1 Timer end value register 1 Timer start value register 1 Timer control register 1 Table 16.4 Address (Hex) 005B 005A 0059 0058 Timer0 registers Register TCVR TEVR TSVR TCR Description Timer current value register 0 Timer end value register 0 Timer start value register 0 Timer control register 0 16.4 Bus switch unit registers Address (Hex) 0055 0054 0053 0052 0051 0050 Register YER1 XER1 IER1 YER0 XER0 IER0 Description External Y-bus control register 1 External X-bus control register 1 External I-bus control register 1 External Y-bus control register 0 External X-bus control register 0 External I-bus control register 0 16.5 System control registers Address (Hex) 004B 004A 0049 0048 Register DMAR INTR PICR CMR Description DMA management register Interrupt vector register Port/interrupt interface control register Clock management register 59/66 ST18952 16.6 DMA controller registers Address (Hex) 0042 0041 0040 003F 003E 003D 003C 003B 003A 0039 0038 0037 0036 0035 0034 0033 0032 0031 0030 Register DAIC DMS DGC DCC3 DCC2 DCC1 DCC0 DIC3 DIC2 DIC1 DIC0 DCA3 DCA2 DCA1 DCA0 DIA3 DIA2 DIA1 DIA0 Description DMA address / interrupt control DMA mask sensitivity DMA general control DMA channel 3 current count DMA channel 2 current count DMA channel 1 current count DMA channel 0 current count DMA channel 3 initial count DMA channel 2 initial count DMA channel 1 initial count DMA channel 0 initial count DMA channel 3 current address DMA channel 2 current address DMA channel 1 current address DMA channel 0 current address DMA channel 3 initial address DMA channel 2 initial address DMA channel 1initial address DMA channel 0 initial address 16.7 Interrupt controller registers 002C 002B 002A 0029 0028 0027 0026 0025 0024 0023 0022 0021 0020 ISR ISPR IPR IMR ICR IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0 Interrupt status register Interrupt stack pointer register Interrupt priority register Interrupt mask/sensitivity register Interrupt control register Interrupt vector 7 address Interrupt vector 6 address Interrupt vector 5 address Interrupt vector 4 address Interrupt vector 3 address Interrupt vector 2 address Interrupt vector 1 address Interrupt vector 0 address 60/66 ST18952 16.8 Emulation unit registers Address (Hex) 0018 0017 0016 0015 0014 0013 0012 0011 0010 Register PCB BPC BP3 BP2 BP1 BP0 BC1 BC0 ECS Description PC trace buffer Breakpoint counter Breakpoint register 3 Breakpoint register 2 Breakpoint register 1 Breakpoint register 0 Breakpoint control register 1 Breakpoint control register 0 EMU control and status register 16.9 D950Core control registers Address (Hex) 0007 0006 0005 0004 0003 0002 0001 0000 Register PCSR PCDR PIR POR MY BY MX BX Description Port control sensitivity register Port control direction register Port input register Port output register Y-memory space modulo max address Y-memory space modulo base address X-memory space modulo max address X-memory space modulo base address 61/66 ST18952 17 ST18952 Package Specifications 17.1 208 pin PQFP pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 IAE<15> IAE<14> IAE<13> IAE<12> IAE<11> GND VDD IAE<10> IAE<9> IAE<8> IAE<7> IAE<6> IAE<5> IAE<4> IAE<3> IAE<2> IAE<1> IAE<0> GND VDD IDE<15> IDE<14> IDE<13> IDE<12> IDE<11> IDE<10> IDE<9> IDE<8> VDD IDE<7> IDE<6> GND VDD IDE<5> IDE<4> IDE<3> 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 DMACK0_STD0 DMACK1_SFS0 DMACK2_STD1 YAE<0> YAE<1> YAE<2> YAE<3> VDD GND YAE<4> YAE<5> YAE<6> YAE<7> YAE<8> YAE<9> YAE<10> YAE<11> YAE<12> YAE<13> VDD GND YAE<14> YAE<15> YBSE VDD GND YRDE YWRE YDE<0> GND VDD VDD GND YDE<1> YDE<2> YDE<3> 105 DTACK 106 ED_XDE<0> 107 ED_XDE<1> 108 ED_XDE<2> 109 VDD 110 GND 111 ED_XDE<3> 112 EXTAL 113 XTAL 114 GND 115 VDD 116 ED_XDE<4> 117 ED_XDE<5> 118 ED_XDE<6> 119 VDD 120 GND 121 ED_XDE<7> 122 ED_XDE<8> 123 ED_XDE<9> 124 VDD 125 GND 126 ED_XDE<10> 127 ED_XDE<11> 128 ED_XDE<12> 129 ED_XDE<13> 130 ED_XDE<14> 131 ED_XDE<15> 132 XBSE 133 XRDE_EXRD 134 XWRE_EXWR 135 EIRD 136 EIWR 137 VDD 138 GND 139 EYRD 140 EYWR 157 EA_XAE<11> 158 EA_XAE<12> 159 EA_XAE<13> 160 EA_XAE<14> 161 GND 162 VDD 163 EA_XAE<15> 164 VCI 165 TMS 166 TDO 167 TDI 168 TCK 169 GND 170 VDD 171 VDD 172 GND 173 STACKY 174 STACKX 175 SNAP 176 TRST 177 RESET_OUT 178 RESET 179 LP 180 LPACK 181 P_ITRQ<7> 182 GND 183 VDD 184 P_ITRQ<6> 185 P_ITRQ<5> 186 P_ITRQ<4> 187 P_ITRQ<3> 188 P_ITRQ<2> 189 P_ITRQ<1> 190 P_ITRQ<0> 191 HOLD 192 HOLDACK 62/66 ST18952 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 IDE<2> GND VDD IDE<1> GND IDE<0> IWRE IRDE IBSE DMARQ3_SCK1 DMARQ2_SRD1 GND VDD DMARQ1_SCK0 DMARQ0_SRD0 DMACK3_SFS1 89 90 91 92 93 94 95 96 97 98 YDE<4> YDE<5> YDE<6> VDD GND YDE<7> YDE<8> VDD GND YDE<9> 141 CLKOUT 142 INCYCLE 143 MCLK 144 EA_XAE<0> 145 EA_XAE<1> 146 EA_XAE<2> 147 EA_XAE<3> 148 EA_XAE<4> 149 EA_XAE<5> 150 EA_XAE<6> 151 VDD 152 GND 153 EA_XAE<7> 154 EA_XAE<8> 155 EA_XAE<9> 156 EA_XAE<10> 193 GND 194 VDD 195 GND 196 VDD 197 ERQ 198 IDT_EN 199 MODE 200 IDLE 201 HALTACK 202 CLK_MODE 203 AYEBP 204 GND 205 VDD 206 AXEBP 207 AIEBP_SCAN_EN 208 IRD_WR 99 YDE<10> 100 YDE<11> 101 YDE<12> 102 YDE<13> 103 YDE<14> 104 YDE<15> 17.2 208 pin PQFP package dimensions Table 17.1 REF. MIN A A1 A2 B C D D1 D3 E E1 E3 e K L L1 Notes 1: Lead finish to be 85 Sn/15 Pb solder plate. 0d 0.45 0.25 3.20 0.17 0.09 30.60 28.00 25.50 30.60 28.00 25.50 0.50 3.5d 0.60 1.30 7d 0.75 3.40 3.60 0.27 0.20 208 pin PQFP package dimensions CONTROL DIM. mm NOM MAX 4.10 63/66 ST18952 Figure 17.1 208 pin PQFP package dimensions 64/66 ST18952 18 Device ID The identification code for the ST18952 is #m52BC041, where m is a manufacturing revision number reserved by SGS-THOMSON. bit 31 Mask rev reserved ST18 family Variant bit 0 SGS-THOMSON manufacturers id C 0 4 1 1) 0101001010111100000001000001 5 2 B 1) Defined as 1 in IEEE 1149.1 standard. 19 Ordering Information Device ST18952X66S Package 208 pin plastic quad flat pack (PQFP) For further information contact your local SGS-THOMSON sales office. 20 Revision History This is revision 1 of this datasheet the differences between revision 1 and revision 0 are: Clarification of SIO0 and SIO1 register addresses in "SIO registers" on page 36. Refomatting of the presentation of the registers; the bit functions have be put into tables. Addition of for PCSR and PCDR register information "D950Core registers" on page 14. Addition of information for "DMAR: DMA management register" on page 44. 65/66 Index of Registers C CMR Clock management register SER SIO Enable register 38 38 40 44 24 SFR SIO Frequency register D DAIC Address/interrupt control register SRDR SIO Receive data register DGC General control register SSR SIO Status register 24 43 25 39 40 DMAR DMA management register STDR SIO Transmit data register DMS Mask sensitivity control register T TCR0-1 Timer control register I ICR Interrupt control register 31 33 TCVR0-1 27 20 Timer current value register IER0/1 Instruction memory control registers TEVR0-1 Timer end value register 33 32 20 20 IMR Interrupt mask/sensitivity register TSVR0-1 Timer start value register 29 INTR Interrupt vector register X XER0/1 X-memory space control registers 43 29 30 IPR Interrupt priority register Y YER0/1 Y-memory space control registers ISPR Interrupt stack pointer register ISR Interrupt status register 30 27 IVO0-7 Interrupt vector0-7 address registers P PCDR Port control direction 14 14 42 36 PCSR Port Control Sensitivity PICR Port/interrupt control register S SCOR SIO sequence control register SCR SIO control register 36 65/66 3 Notes Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THO MSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THO MSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express writt en approval of SGS-THOMSON Microelectronics. (c)1997 SGS-THOMS ON Microelectronics - All rights reserved. SGS-THOMS ON Microelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 66/66 |
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